SH7729R Datasheet, PDF(602/855 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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SH7729R Datasheet, PDF (602/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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17.1.2 Block Diagram

Figure 17.1 shows a block diagram of the SCIF.

Module data bus

Internal

data bus

RxD

TxD

SCK

SCFRDR2

(16

stages)

Receive

buffer

SCRSR

SCFTDR2

(16

stages)

SCPCR

SCFDR

SCFDR2

SCFCR2

SCBRR

SCSSR2

Transmit

buffer

SCSCR2

SCSMR2

Baud rate

generator

SCTSR

Transmit/

receive

control

Parity generation

Clock

Parity check

External clock

SCIF

PÏ

PÏ/4

PÏ/16

PÏ/64

TEI

TXI

RXI

BRI

Legend

SCRSR: Receive shift register

SCFRDR: Receive FIFO data register

SCTSR: Transmit shift register

SCFTDR2: Transmit FIFO data register

SCSMR2: Serial mode register

SCSCR2: Serial control register

SCSSR2: Serial status register

SCBRR2: Bit rate register

SCFCR2: FIFO control register

SCFDR2: FIFO data count register

SCPDR: Port SC data register

SCPCR: Port SC control register

Figure 17.1 Block Diagram of SCIF

Rev. 5.0, 09/03, page 556 of 806

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