SH7729R Datasheet, PDF (624/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

17.2.9 FIFO Control Register (SCFCR)
Bit:
Initial value:
R/W:
7
RTRG1
0
R/W
6
RTRG0
0
R/W
5
TTRG1
0
R/W
4
TTRG0
0
R/W
3
MCE
0
R/W
2
1
TFRST RFRST
0
0
R/W R/W
0
LOOP
0
R/W
The FIFO control register (SCFCR) resets the quantity of data in the transmit and receive FIFO
registers, sets the trigger data quantity, and contains an enable bit for loop-back testing. SCFCR
can always be read and written to by the CPU. It is initialized to H'00 by a reset, by the module
standby function, and in standby mode.
Bits 7 and 6—Receive FIFO Data Trigger (RTRG1, RTRG0): Set the quantity of receive data
which sets the receive data full (RDF) flag in the serial status register (SCSSR). The RDF flag is
set when the quantity of receive data stored in the receive FIFO register (SCFRDR) becomes equal
or greater than the set trigger number shown below.
Bit 7: RTRG1
0
0
1
1
Bit 6: RTRG0
0
1
0
1
Receive Trigger Number
1
4
8
14
(Initial value)
Bits 5 and 4—Transmit FIFO Data Trigger (TTRG1, TTRG0): Set the quantity of remaining
transmit data which sets the transmit FIFO data register empty (TDFE) flag in the serial status
register (SCSSR). The TDFE flag is set when the quantity of transmit data in the transmit FIFO
data register (SCFTDR) becomes less than the set trigger number shown below.
Bit 5: TTRG1
Bit 4: TTRG0
Transmit Trigger Number
0
0
8 (8)^*
0
1
4 (12)
1
0
2 (14)
1
1
1 (15)
Note: * Initial value. Values in parentheses mean the number of empty bits in SCFTDR when the
TDFE flag is set to 1.
Rev. 5.0, 09/03, page 578 of 806