SH7729R Datasheet, PDF (232/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 4—ADI Interrupt Request (ADIR): Indicates whether an ADI (ADC) interrupt request has
been generated.
Bit 4: ADIR
0
1
Description
ADI interrupt request not generated
ADI interrupt request generated
(Initial value)
Bit 3—TXI2 Interrupt Request (TXI2R): Indicates whether a TXI2 (SCIF) interrupt request has
been generated.
Bit 3: TXI2R
0
1
Description
TXI2 interrupt request not generated
TXI2 interrupt request generated
(Initial value)
Bit 2—BRI2 Interrupt Request (BRI2R): Indicates whether a BRI2 (SCIF) interrupt request has
been generated.
Bit 2: BRI2R
0
1
Description
BRI2 interrupt request not generated
BRI2 interrupt request generated
(Initial value)
Bit 1—RXI2 Interrupt Request (RXI2R): Indicates whether an RXI2 (SCIF) interrupt request
has been generated.
Bit 1: RXI2R
0
1
Description
RXI2 interrupt request not generated
RXI2 interrupt request generated
(Initial value)
Bit 0—ERI2 Interrupt Request (ERI2R): Indicates whether an ERI2 (SCIF) interrupt request
has been generated.
Bit 0: ERI2R
0
1
Description
ERI2 interrupt request not generated
ERI2 interrupt request generated
(Initial value)
Rev. 5.0, 09/03, page 186 of 806