SH7729R Datasheet, PDF (495/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

13.4.2 Status Flag Clearing Timing
The status flag can be cleared by writing 0 from the CPU. Figure 13.9 shows the timing.
TCR write cycle
T₁
T₂
T₃
Pφ
Peripheral address bus
TCR address
UNF
Figure 13.9 Status Flag Clearing Timing
13.4.3 Interrupt Sources and Priorities
The TMU produces underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, an interrupt is requested. Codes are set in the interrupt event
registers (INTEVT, INTEVT2) for these interrupts and interrupt handling occurs according to the
codes.
The relative priorities of channels can be changed using the interrupt controller (see section 4,
Exception Handling, and section 7, Interrupt Controller (INTC)). Table 13.3 lists TMU interrupt
sources.
Table 13.3 TMU Interrupt Sources
Channel
0
1
2
2
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2
Priority
High
Low
Rev. 5.0, 09/03, page 449 of 806