SH7729R Datasheet, PDF (221/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.3 INTC Registers
7.3.1 Interrupt Priority Registers A to E (IPRA–IPRE)
Interrupt priority registers A to E (IPRA to IPRE) are 16-bit readable/writable registers in which
priority levels from 0 to 15 are set for on-chip peripheral module, IRQ, and PINT interrupts. These
registers are initialized to H'0000 by a power-on reset or manual reset, but are not initialized in
standby mode.
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 7.7 lists the relationship between the interrupt sources and the IPRA—IPRE bits.
Table 7.7 Interrupt Request Sources and IPRA–IPRE
Register
Bits 15 to 12
Bits 11 to 8
Bits 7 to 4
IPRA
TMU0
TMU1
TMU2
IPRB
WDT
REF
SCI0
IPRC
IRQ3
IRQ2
IRQ1
IPRD
PINT0 to PINT7 PINT8 to PINT15 IRQ5
IPRE
DMAC
IrDA
SCIF
Note: * Always read as 0. Only 0 should be written.
Bits 3 to 0
RTC
Reserved^*
IRQ0
IRQ4
ADC
As shown in table 7.7, on-chip peripheral module, IRQ, or PINT interrupts are assigned to four 4-
bit groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to
0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking
is requested); H'F is priority level 15 (the highest level). A reset initializes IPRA–IPRE to H'0000.
Rev. 5.0, 09/03, page 175 of 806