SH7729R Datasheet, PDF (206/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Area 1, 64 Mbytes
4000000
I/O register space
16 Mbytes
5000000
5020000
X/Y Memory
6000000
Reserved area
16 Mbytes
Reserved area
32 Mbytes
7FFFFFF
128-kbyte X/Y Memory
5000000
X-ROM/X-RAM
Reserved space
5007000
5008FFF
X-RAM, 8 kbytes
5010000
X-ROM/X-RAM
Reserved space
Y-ROM/X-RAM
Reserved space
5017000
Y-RAM, 8 kbytes
5018FFF
Y-ROM/X-RAM
Reserved space
501FFFF
Figure 6.2 X/Y Memory Physical Address Mapping
6.3 X/Y Memory Access from DSP
The X/Y memory can be accessed by the DSP through the X bus and Y bus. Accesses via the X
bus/Y bus are always 16-bit, while accesses via the L bus are either 16-bit or 32-bit. Accesses via
the X bus and Y bus cannot be specified simultaneously.
6.4 X/Y Memory Access from DMAC
The X/Y memory also exists on the I bus and can be accessed by the DMAC. DMAC access uses
an 8-/16-/32-bit unit. If the I bus accesses X/Y memory simultaneously with an access from the X
bus/Y bus or L bus, the I bus master has a higher priority.
When accessing X/Y memory from the DMAC, use physical addresses in the range H'05000000 to
H'05FFFFFF.
Rev. 5.0, 09/03, page 160 of 806