SH7729R Datasheet, PDF (184/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

 Operations: PC of the instruction immediately after the instruction executed before the
exception occurs is saved to SPC. SR when the exception occurs is saved to SSR. H'5C0 is
set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC =
VBR + H'0100.
4.5.3 Interrupts
1. NMI
 Conditions: NMI pin edge detection
 Operations: PC after the instruction that receives the interrupt are saved to SPC,
respectively. PC after the instruction that receives the interrupt is saved to SPC, and SR at
the point the interrupt is accepted is saved to SSR. H'01C0 is set to INTEVT and
INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to PC =
VBR + H'0600. This interrupt is not masked by the interrupt mask bits in SR and is
accepted with top priority when the BL bit in SR is 0. When the BL bit is 1, the interrupt is
masked. See section 7, Interrupt Controller (INTC), for more information.
2. IRL Interrupts
The value of the interrupt mask bits in SR is lower than the IRL3–IRL0 level and the BL bit in
SR is 0. The interrupt is accepted at an instruction boundary.
 Operations: The PC value after the instruction at which the interrupt is accepted is saved to
SPC. SR at the time the interrupt is accepted is saved to SSR. The code corresponding to
the IRL3–IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as
H'200 + [IRL3–IRL0] × H'20. See table 7.5, for the corresponding codes. The BL, MD, and
RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not
set in the interrupt mask bits in SR. See section 7, Interrupt Controller (INTC), for more
information.
3. IRQ Pin Interrupts
 Conditions: The IRQ pin is asserted, the interrupt mask bits in SR are lower than the IRQ
priority level, and the BL bit in SR is 0. The interrupt is accepted at an instruction
boundary.
 Operations: The PC value after the instruction at which the interrupt is accepted is saved to
SPC. SR at the point the interrupt is accepted is saved to SSR. The code corresponding to
the interrupt source is set in INTEVT and INTEVT2. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to VBR + H'0600. The received level is not set in the interrupt
mask bits in SR. See section 7, Interrupt Controller (INTC), for more information.
Rev. 5.0, 09/03, page 138 of 806