SH7729R Datasheet, PDF (45/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 20.22 Port L Data Register (PLDR) Read/Write Operation ............................................. 652
Table 20.23 SC Port Register ..................................................................................................... 653
Table 20.24 Read/Write Operation of the SC Port Data Register (SCPDR) .............................. 655
Table 21.1 A/D Converter Pins................................................................................................. 659
Table 21.2 A/D Converter Registers......................................................................................... 660
Table 21.3 Analog Input Channels and A/D Data Registers .................................................... 661
Table 21.4 A/D Conversion Time (Single Mode)..................................................................... 673
Table 21.5 Analog Input Pin Ratings........................................................................................ 677
Table 21.6 Relationship between Access Size and Read Data ................................................. 677
Table 22.1 D/A Converter Pins................................................................................................. 680
Table 22.2 D/A Converter Registers......................................................................................... 680
Table 23.1 UDI Registers ......................................................................................................... 687
Table 23.2 UDI Commands ...................................................................................................... 688
Table 23.3 SH7729R Pins and Boundary Scan Register Bits ................................................... 689
Table 23.4 Reset Configuration ................................................................................................ 696
Table 24.1 Absolute Maximum Ratings ................................................................................... 701
Table 24.2 DC Characteristics .................................................................................................. 703
Table 24.3 Permissible Output Current Values ........................................................................ 706
Table 24.4 Operating Frequency Range ................................................................................... 706
Table 24.5 Clock Timing .......................................................................................................... 707
Table 24.6 Control Signal Timing ........................................................................................... 713
Table 24.7 Bus Timing ............................................................................................................. 716
Table 24.8 Peripheral Module Signal Timing........................................................................... 749
Table 24.9 UDI-Related Pin Timing......................................................................................... 753
Table 24.10 A/D Converter Characteristics................................................................................ 757
Table 24.11 D/A Converter Characteristics................................................................................ 757
Table A.1 Pin States during Resets, Power-Down States, and Bus-Released State................. 759
Table A.2 Pin Specifications ................................................................................................... 763
Table A.3 Pin States (Ordinary Memory/Little Endian).......................................................... 769
Table A.4 Pin States (Ordinary Memory/Big Endian)............................................................. 771
Table A.5 Pin States (Burst ROM/Little Endian) .................................................................... 773
Table A.6 Pin States (Burst ROM/Big Endian) ....................................................................... 775
Table A.7 Pin States (Synchronous DRAM/Little Endian) ..................................................... 777
Table A.8 Pin States (Synchronous DRAM/Big Endian) ........................................................ 778
Table A.9 Pin States (PCMCIA/Little Endian)........................................................................ 779
Table A.10 Pin States (PCMCIA/Big Endian) .......................................................................... 781
Table B.1 Memory-Mapped Control Registers ....................................................................... 783
Table B.2 Register Bits ........................................................................................................... 789
Table C.1 SH7729R Models ................................................................................................... 802
Rev. 5.0, 09/03, page xlv of xlvi