SH7729R Datasheet, PDF (617/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

17.2.8 Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The SCBRR setting is calculated as follows:
Asynchronous mode:
N=
Pφ
× 10⁶ – 1
64 × 2^{2n – 1} × B
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 17.3.)
Table 17.3 SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
Note: The bit rate error is given by the following formula:
Error (%) =
Pφ
× 10⁶ − 1 × 100
(N+1) × 64 × 2^2n−1 × B
Rev. 5.0, 09/03, page 571 of 806