SH7729R Datasheet, PDF (365/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 11.2.4, Wait
State Control Register 2 (WCR2).
The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing
shown in figure 11.10.
CKIO
T₁
Tw
T₂
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn
D31 to D0
BS
Figure 11.10 Basic Interface Wait Timing (Software Wait Only)
When software wait insertion is specified by WCR2, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 11.11. A 2-cycle wait is specified as a software
wait. Sampling is performed at the transition from the Tw state to the T₂ state; therefore, if the
WAIT signal has no effect if asserted in the T₁ cycle or the first Tw cycle.
Rev. 5.0, 09/03, page 319 of 806