SH7729R Datasheet, PDF (13/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section
10.3 Clock Operating
Modes
Table 10.4 Available
Combinations of Clock
Mode and FRQCR
Values
10.5.3 Notes on
Changing the
Frequency
10.8.2 Changing the
Frequency
Page
256
259
265
11.1.1 Features

11.2.5 Individual
292
Memory Control
Register (MCR)
293
Description
Cautions 4 to 6 deleted
Newly added
Description added
5.The counter stops at a value of H'00 or H'01. The stop value
depends on the clock ratio.
If the following three conditions are all met, FRQCR should not be
changed when a transfer using the DMAC is in progress.
• Bits IFC2 to IFC0 are changed.
• Bits STC2 to STC0 are not changed.
• The clock ratio is other than Iφ:Bφ = 1:1.
Refresh function description deleted
Description added
Bit 7—Synchronous DRAM Bank Active (RASD): Specifies
whether synchronous DRAM is used in bank active mode or auto-
precharge mode. Set auto-precharge mode when areas 2 and 3
are both designated as synchronous DRAM space.
The bank active mode should not be used unless the bus width
for all areas is 32 bits.
Bit table amended
Bits 6 to 3—Address Multiplex (AMX3, AMX2, AMX1, AMX0)
Bit6: Bit5: Bit 4:
AMX3 AMX2 AMX1
0
1
0
1
Bit 3:
AMX0 Description
0
The row address begins with
A9 (The A9 value is output at
A1 when the row address is
output. 1M × 16-bit × 4-bank
products)
1
The row address begins with
A10 (The A10 value is output at
A1 when the row address is
output. 2M × 8-bit × 4-bank
products ,2M × 16-bit × 4-bank
products)
1 The row address begins with
A9 (The A9 value is output at
A1 when the row address is
output. 512k × 32-bit × 4-bank
products)
Rev. 5.0, 09/03, page xiii of xlvi