SH7729R Datasheet, PDF (76/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

2.1.3 System Registers
The SH7729R has four system registers, MACL, MACH, PR, and PC (figure 2.6).
31
MACH
MACL
31
PR
31
PC
0
Multiply and accumulate high and low registers
(MACH/L)
Store the results of multiplicationand accumulation
operations.
0
Procedure register (PR)
Stores the subroutine procedure return address.
0
Program counter (PC)
Indicates the start address of the current instruction.
Figure 2.6 System Registers
The DSR, A0, X0, X1, Y0, and Y1 registers are also treated as system registers. Therefore,
instructions for data transfer between general registers and system registers are supported for these
registers.
2.1.4 DSP Registers
The SH7729R has eight data registers and one status register as DSP registers (figure 2.7). The
data registers are 32-bit width with the exception of registers A0 and A1. Registers A0 and A1
include 8 guard bits (fields A0G and A1G), giving them a total width of 40 bits.
Three kinds of operation access the DSP data registers. The first is DSP data processing. When a
DSP fixed-point data operation uses A0 or A1 as the source register, it uses the guard bits (bits
39–32). When it uses A0 or A1 as the destination register, guard bits 39–32 are valid. When a DSP
fixed-point data operation uses a DSP register other than A0 or A1 as the source register, it sign-
extends the source value to bits 39–32. When it uses one of these registers as the destination
register, bits 39–32 of the result are discarded.
The second kind of operation is an X or Y data transfer operation, “MOVX.W MOVY.W”. This
operation accesses the X and Y memories through the 16-bit X and Y data buses (figure 2.8). The
register to be loaded or stored by this operation always comprises the upper 16 bits (bits 31–16).
X0 or X1 can be the destination of an X memory load and Y0 or Y1 can be the destination of a Y
memory load, but no other register can be the destination register in this operation. When data is
read into the upper 16 bits of a register (bits 31–16), the lower 16 bits of the register (bits 15–0)
are automatically cleared.
A0 and A1 can be stored in the X or Y memory using the X or Y data transfer instructions
MOVX.W and MOVY.W, but no other registers can be stored.
Rev. 5.0, 09/03, page 30 of 806