SH7729R Datasheet, PDF (293/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO, CKIO2^*6
CA
RESETP
STATUS
Standby^*2 Normal^*3
Standby^*2
Undefined
Reset^*1
WDT operation
0−10 Bcyc^*4
2 Rcyc or more^*5
Notes: 1. Reset: HH (STATUS1 high, STATUS0 high)
2. Standby: LH (STATUS1 low, STATUS0 high)
3. Normal: LL (STATUS1 low, STATUS0 low)
4. Bcyc: Bus clock cycle
5. Rcyc: EXTAL2 (32.768 kHz) cycle
6. CKIO2 output can only be used in clock modes 0, 1, and 2.
Figure 9.11 Hardware Standby Mode Timing
(When CA Goes Low during WDT Operation on Standby Mode Cancellation)
Rev. 5.0, 09/03, page 247 of 806