SH7729R Datasheet, PDF (107/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Type
Branch
instructions
System
control
instructions
Total:
Kinds of
Instruction
9
Op Code
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
15
CLRT
CLRMAC
CLRS
LDC
LDS
LDTLB
NOP
PREF
RTE
SETS
SETT
SLEEP
STC
STS
TRAPA
68
Function
Number of
Instructions
Conditional branch, delayed conditional 11
branch (T = 0)
Conditional branch, delayed conditional
branch (T = 1)
Unconditional branch
Unconditional branch
Branch to subroutine procedure
Branch to subroutine procedure
Unconditional branch
Branch to subroutine procedure
Return from subroutine procedure
T bit clear
75
MAC register clear
S bit clear
Load into control register
Load into system register
PTEH/PTEL load into TLB
No operation
Data prefetch to cache
Return from exception handling
S bit setting
T bit setting
Transition to power-down mode
Store from control register
Store from system register
Trap exception handling
188
Rev. 5.0, 09/03, page 61 of 806