SH7729R Datasheet, PDF (199/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

1. Address array access
Address specification
Read access
31
24
1111 0000
23
14
*^{…………}*
13 12
W
11
Entry
Write access
31
24
1111 0000
23
14
*^{…………}*
13 12
W
11
Entry
4
3
2
0
0* * *
4
3
2
0
A_{* * *}
Data specification
31 30 29
0 0 0 Address tag (31−10)
10 9
4
LRU
3
2
XX
1
0
UV
2. Data array access (both read and write accesses)
Address specification
31
24
1111 0001
23
14
*^{…………}*
13 12
W
11
Entry
4
3
21
0
L
**
Data specification
31
0
Longword
X: 0 for read, don't care for write
*: Don't care bit
Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access
Rev. 5.0, 09/03, page 153 of 806