SH7729R Datasheet, PDF (686/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

20.6.2 Port E Data Register (PEDR)
Bit:
Initial value:
R/W:
7
PE7DT
0
R/W
6
PE6DT
0
R/W
5
PE5DT
0
R/W
4
PE4DT
0
R/W
3
PE3DT
0
R/W
2
PE2DT
0
R/W
1
PE1DT
0
R/W
0
PE0DT
0
R/W
The port E data register (PEDR) is an 8-bit readable/writable register that stores data for pins
PTE7 to PTE0. Bits PE7DT to PE0DT correspond to pins PTE7 to PTE0. When the pin function is
general output port, if the port is read the value of the corresponding PEDR bit is returned directly.
When the function is general input port, if the port is read the corresponding pin level is read.
Table 20.10 shows the function of PEDR.
PEDR is initialized to H'00 by a power-on reset, after which the general input port function (pull-
up MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains
its previous value in standby mode and sleep mode, and in a manual reset.
Table 20.10 Port E Data Register (PEDR) Read/Write Operations
PEnMD1
0
1
PEnMD0
0
1
0
1
Pin State
Other function
(See table 19.1)
Output
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
Read
PEDR value
PEDR value
Pin state
Pin state
Write
Value is written to PEDR, but does not
affect pin state
Write value is output from pin
Value is written to PEDR, but does not
affect pin state
Value is written to PEDR, but does not
affect pin state
(n = 0 to 7)
Rev. 5.0, 09/03, page 640 of 806