SH7729R Datasheet, PDF (180/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• TLB invalid exception
 Conditions: Comparison of TLB addresses shows address match but the TLB entry valid
bit (V) is 0.
 Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
PC and SR of the instruction that generated the exception are saved to SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
• TLB exception/CPU address error in repeat loop
 Conditions: TLB miss, TLB invalid or CPU address error in the last several instructions of
repeat loop (see section 3.5.6, MMU Exception in Repeat Loop)
 Operations: TEA, PTEH and RC bit in MMUCR are set in the way of the type of
exception.
SR of the instruction that generated the exception is saved to SSR, but SPC is not the PC of the
instruction that generated the exception. A repeat loop cannot be restarted after returning from
the exception handler. In order to complete a repeat loop, ensure that a TLB exception or CPU
address error does not occur in the last several instructions of the repeat loop (see section 3.5.6,
MMU Exception in Repeat Loop). If a TLB exception or CPU address error occurs in the last
several instructions of a repeat loop, H'070 is set in EXPEVT. The BL, MD, and RB bits in SR
are set to 1 and a branch occurs to PC = VBR + H'0100.
• Initial page write exception
 Conditions: A hit occurred to the TLB for a store access, but the TLB entry data bit (D) is
0.
This occurs for initial writes to the page registered by the load.
 Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bit in MMUCR.
PC and SR of the instruction that generated the exception are saved to SPC and SSR,
respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a
branch occurs to PC = VBR + H'0100.
Rev. 5.0, 09/03, page 134 of 806