SH7729R Datasheet, PDF (244/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.2 Break Address Mask Register A (BAMRA)
Bit: 31
30
29
28
27
26
25
24
BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
19
18
17
16
BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
BAMRA is a 32-bit readable/writable register that specifies bits masked in the break address
specified by BARA. BAMRA is initialized to H'00000000 by a power-on reset.
Bits 31 to 0—Break Address Mask Register A31 to A0 (BAMA31 to BAMA0): Specify bits
masked in the channel A break address bits specified by BARA (BAA31–BAA0).
Bits 31–0:
BAMAn
0
1
n = 31–0
Description
Break address bit BAAn of channel A is included in the break condition
(Initial value)
Break address bit BAAn of channel A is masked and is not included in the break
condition
Rev. 5.0, 09/03, page 198 of 806