SH7729R Datasheet, PDF (771/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
A25 to A16
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
Tr
Trw
Trw
Tc1
Tcw
Td1
(Tpc)
(Tpc)
tAD
Row address
tAD
Row address
tAD
Row address
tCSD3
tRWD
tRASD2 tRASD2
tDQMD
tAD
tAD
tAD
Read A
command
tAD
Column address
tAD
tCSD3
tRWD
tCASD2 tCASD2
tDQMD
tRDS2 tRDH2
tBSD
tBSD
CKE
DACKn
tDAKD1
(High)
tDAKD1
Figure 24.23 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1)
Rev. 5.0, 09/03, page 725 of 806