SH7729R Datasheet, PDF (88/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Addressing
Mode
Register
indirect with
displacement
Instruction
Format Effective Address Calculation Method
@(disp:4,
Rn)
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
Rn
disp
+
(zero-extended)
×
Rn
+ disp × 1/2/4
Calculation
Formula
Byte: Rn + disp
Word: Rn + disp ×
2
Longword: Rn +
disp × 4
1/2/4
Indexed
@(R0, Rn) Effective address is sum of register Rn and R0
register indirect
contents.
Rn
Rn + R0
+
Rn + R0
GBR indirect
with
displacement
R0
@(disp:8,
GBR)
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
GBR
Byte: GBR + disp
Word: GBR + disp
×2
Longword: GBR +
disp × 4
disp
+
(zero-extended)
×
GBR
+ disp × 1/2/4
1/2/4
Rev. 5.0, 09/03, page 42 of 806