SH7729R Datasheet, PDF (449/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
A25 to A0
CSn
D31 to D0
RD
WEn
Transfer
+4
source address
DACKn
+8
+12
Figure 12.13 Example of DMA Transfer Timing in Single Address Mode
(External Memory Space (Ordinary Memory) → External Device with DACK)
Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of
CHCR0–CHCR3.
• Cycle-Steal Mode
In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (8-, 16-, or
32-bit unit) DMA transfer. When another transfer request occurs, the bus is obtained from the
other bus master and transfer is performed for one transfer unit. When that transfer ends, the
bus is passed to the other bus master. This is repeated until the transfer end conditions are
satisfied.
In the cycle-steal mode, transfer areas are not affected regardless of the transfer request source,
transfer source, and transfer destination settings. Figure 12.14 shows an example of DMA
transfer timing in cycle-steal mode. Transfer conditions shown in the figure are:
Dual address mode
DREQ level detection
DREQ
Bus returned to CPU
Bus cycle
CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU
Read Write
Read Write
Figure 12.14 Example of Transfer in Cycle-Steal Mode
Rev. 5.0, 09/03, page 403 of 806