SH7729R Datasheet, PDF (519/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figures 15.2, 15.3, and 15.4 show block diagrams of the SCI I/O port pins.
SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR.
For details, see section 15.2.8, SC Port Control Register (SCPCR)/SC Port Data Register
(SCPDR).
SCPT[1]/SCK0
Reset
R
D
SCP1MD0
Q
C
PCRW
Reset
R
QD
SCP1MD1
C
PCRW
Reset
R
QD
SCP1DT1
C
PDRW
Internal data bus
SCI
Clock input enable
Output enable
Serial clock output
PDRR^*
Serial clock input
Legend
PDRW: SCPDR write
PDRR: SCPDR read
PCRW: SCPCR write
Note: * When reading the SCK0 pin, clear the C/A bit in SCSMR and the CKE1 and CKE0
bits in SCSCR to 0, and set the SCP1MD1 bit in SCPCR to 1 (see section 15.2.8,
SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR)).
Figure 15.2 SCPT[1]/SCK0 Pin
Rev. 5.0, 09/03, page 473 of 806