SH7729R Datasheet, PDF (74/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

31
31
31
31
31
31
31
MOD
SSR
SPC
GBR
VBR
RS
RE
16 15
ME(Modulo end address)
0
Saved status register
0
Saved program counter
0
Global base register
0
Vector base register
0
Repeat start register
0
Repeat end register
0
MS(Modulo start address) Modulo register
Saved status register (SSR)
Stores current SR value at time of exception and returns value to SR when returning to instruction
stream from exception or interrupt handler.
Saved program counter (SPC)
Stores current PC value at time of exception to indicate return address on completion of exception
handling.
Global base register (GBR)
Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is used for
data transfer and logical operations on the on-chip peripheral module register area.
Vector base register (VBR)
Stores base address of exception vector area.
Repeat start register (RS)
Used in DSP mode only. Indicates start address of repeat loop.
Repeat end register (RE)
Used in DSP mode only. Indicates end address of repeat loop.
Modulo register(MOD)
Used in DSP mode only.
MD[31:16] [ME]: Modulo end address, MD[15:0][MS]: Modulo start address.
In X/Y operand address generation, the CPU compares the address with ME, and if it is the same,
loads MS in either the X or Y operand address register (depending on bits DMX and DMY in the SR
register).
Figure 2.5 Control Registers (cont)
Rev. 5.0, 09/03, page 28 of 806