SH7729R Datasheet, PDF (288/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Standby to Manual Reset
Oscillation stops
Reset
CKIO, CKIO2^*6
RESETM^*1
STATUS
Normal^*4
Standby^*3
Reset^*2
Normal^*4
0 to 20 Bcyc^*5
Notes: 1. When standby mode is cleared with a manual reset, the WDT does not count.
Keep RESETM low during the PLL’s oscillation settling time.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Standby: LH (STATUS1 low, STATUS0 high)
4. Normal: LL (STATUS1 low, STATUS0 low)
5. Bcyc: Bus clock cycle
6. CKIO2 output can only be used in clock modes 0, 1, and 2.
Figure 9.6 Standby to Manual Reset STATUS Output
Rev. 5.0, 09/03, page 242 of 806