SH7729R Datasheet, PDF (446/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

CKIO
A25 to A0
CSn
D31 to D0
Internal
address
bus
Internal
data bus
DMAC
indirect
address
buffer
DMAC
data
buffer
RD
WEn
Transfer
source
address (H)
Transfer
source
address (L)
NOP
Indirect
address
Transfer
destination
address
Indirect
address (H)
Indirect
address (L)
Transfer source
address ^*1
NOP
Transfer source address ^*2
Transfer
data
Transfer
data
Indirect
address
Transfer Transfer
data
data
Indirect
address
Transfer
data
Address read cycle
(1st)
(2nd)
NOP
cycle
Data
read cycle
(3rd)
Data
write cycle
(4th)
Transfer between external memories
Notes: 1. The internal address bus value does not change, and is controlled by the port.
2. The DMAC does not fetch the value until 32-bit data is output to the internal
data bus.
Figure 12.10 Example of Transfer Timing in the Indirect Address Mode
in Dual Address Mode
Rev. 5.0, 09/03, page 400 of 806