SH7729R Datasheet, PDF (96/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 2.14 CPU Instruction Formats
Instruction Format
Source
Operand
Destination
Operand
Sample Instruction
0 type
—
—
NOP
15
0
xxxx xxxx xxxx xxxx
n type
15
xxxx nnnn xxxx
m type
15
xxxx mmmm xxxx
0
xxxx
0
xxxx
—
nnnn: register
MOV T Rn
direct
Control register or nnnn: register
system register direct
STS MACH,Rn
Control register or nnnn: pre-
STC.L SR,@-Rn
system register decrement register
indirect
mmmm: register
direct
Control register or LDC Rm,SR
system register
mmmm: post-
Control register or LDC.L @Rm+,SR
increment register system register
indirect
mmmm: register
—
indirect
JMP @Rm
PC-relative using —
Rm
BRAF Rm
Rev. 5.0, 09/03, page 50 of 806