SH7729R Datasheet, PDF (430/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 1—Transfer End Bit (TE): Set to 1 on completion of the number of data transfers specified
in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.
If data transfer ends due to an NMI interrupt, a DMAC address error, or clearing of the DE bit or
the DME bit in DMAOR before this bit is set to 1, this bit will not be set to 1. Even if the DE bit
is set to 1 while this bit is set to 1, transfer is not enabled.
Bit 1: TE
0
1
Description
Data transfers specified in DMATCR not completed
Clearing conditions: Writing 0 to TE after reading TE = 1
Power-on reset, manual reset
Data transfers specified in DMATCR completed
(Initial value)
Bit 0—DMAC Enable Bit (DE): Enables operation of the corresponding channel.
Bit 0: DE
0
1
Description
Channel operation disabled
Channel operation enabled
(Initial value)
If an auto-request is specified (RS3 to RS0), transfer starts when this bit is set to 1. In an external
request or an internal module request, transfer starts when a transfer request is generated after this
bit is set to 1. Clearing this bit during transfer terminates the transfer.
Even if the DE bit is set, transfer is not enabled if the TE bit is 1, the DME bit in DMAOR is 0, or
the NMIF bit in DMAOR is 1.
Rev. 5.0, 09/03, page 384 of 806