SH7729R Datasheet, PDF (249/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.6 Break Data Register B (BDRB)
Bit:
Initial value:
R/W:
31
BDB31
0
R/W
30
BDB30
0
R/W
29
BDB29
0
R/W
28
BDB28
0
R/W
27
BDB27
0
R/W
26
BDB26
0
R/W
25
BDB25
0
R/W
24
BDB24
0
R/W
Bit:
Initial value:
R/W:
23
BDB23
0
R/W
22
BDB22
0
R/W
21
BDB21
0
R/W
20
BDB20
0
R/W
19
BDB19
0
R/W
18
BDB18
0
R/W
17
BDB17
0
R/W
16
BDB16
0
R/W
Bit:
Initial value:
R/W:
15
BDB15
0
R/W
14
BDB14
0
R/W
13
BDB13
0
R/W
12
BDB12
0
R/W
11
BDB11
0
R/W
10
BDB10
0
R/W
9
BDB9
0
R/W
8
BDB8
0
R/W
Bit:
Initial value:
7
BDB7
0
6
BDB6
0
5
BDB5
0
4
BDB4
0
3
BDB3
0
2
BDB2
0
1
BDB1
0
0
BDB0
0
BDRB is a 32-bit readable/writable register. The control bits XYE and XYS in BBRB select a data
bus for break condition B. If XYE is 0, then BDRB specifies the break data on LDB or IDB. If
XYE is 1, then BDB31–16 specifies the break data on XDB (bits 15–0) and BDB15–0 specifies
the break data on YDB (bits 15–0). However, one of two data buses must be chosen for the break.
BDRB is initialized to H'00000000 by a power-on reset.
XYE = 0
XYE = 1
BDB31–16
L(I) DB31–16
XDB15–0 (XYS = 0)
BDB15–0
L(I) DB15–0
YDB15–0 (XYS = 1)
Rev. 5.0, 09/03, page 203 of 806