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SH7729R Datasheet, PDF (75/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Details of the status register (SR) when STC/LDC instructions are used are shown below.
1. When the DSP is not operating, operation is the same as for the SH-3.
2. In privileged DSP mode, operation is the same as in privileged mode.
3. In user DSP mode, SR can be read with an STC instruction.
4. In user DSP mode, an LDC instruction can be issued for SR, but in this case DSP-related bits
are not write-protected.
Table 2.2 Operation of SR Bits in Each SH-3 DSP Mode
Field
Privileged
Mode
MD = 1 &
DSP = 0
User Mode
MD = 0 &
DSP = 0
Privileged
DSP Mode
MD = 1 &
DSP = 1
User DSP
Mode
MD = 0 &
DSP = 1
Access to
DSP-Related
Bit with
Dedicated
Instruction
Initial Value after
Reset
MD
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
1
instruction
RB
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
1
instruction
BL
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
1
instruction
RC
[11:0]
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: OK SETRC
instruction
instruction
000000000000
DSP
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
0
instruction
DMX
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: OK
0
instruction
DMY
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: OK
0
instruction
Q
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
x
instruction
M
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
x
instruction
I[3:0]
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
instruction
1111
RF[1:0] S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: OK SETRC
x
instruction
instruction
S
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
x
instruction
T
S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG
x
instruction
Legend
S (STC): Store SR to Rn,SR->Rn
L (LDC): Load Rn to Sr,Rn->SR
OK: STC/LDC operation is enabled.
Invalid instruction: Exception occurs when an invalid instruction is executed.
NG: Previous value is retained. No change.
Rev. 5.0, 09/03, page 29 of 806