SH7729R Datasheet, PDF (145/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.3 TLB Functions
3.3.1 Configuration of the TLB
The TLB caches address translation table information located in external memory. The address
translation table stores the physical page number translated from the virtual page number and the
control information for the page, which is the unit of address translation. Figure 3.4 shows the
overall TLB configuration. The TLB is 4-way set associative with 128 entries. There are 32 entries
for each way. Figure 3.5 shows the configuration of virtual addresses and TLB entries.
Ways 0−3
Ways 0−3
Entry 0 VPN(31−17) VPN(11−10) ASID(7−0) V
Entry 1
Entry 0 PPN(28−10) PR(1−0) SZ C D SH
Entry 1
Entry 31
Address array
Entry 31
Data array
Figure 3.4 Overall Configuration of the TLB
Rev. 5.0, 09/03, page 99 of 806