SH7729R Datasheet, PDF (711/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

21.3 Bus Master Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8
bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly
by the bus master, the lower byte is read through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the bus master and the lower-byte value is transferred into TEMP. Next,
when the lower byte is read, the TEMP contents are transferred to the bus master.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed.
Figure 21.2 shows the data flow for access to an A/D data register.
See section 21.7.3, Access Size and Read Data.
Upper byte read
CPU
receives
data H'AA
Bus
interface
Module internal data bus
TEMP
[H'40]
Lower byte read
CPU
receives
data H'40
ADDRn H
[H'AA]
ADDRn L
[H'40]
n = A to D
Bus
interface
Module internal data bus
TEMP
[H'40]
ADDRn H
[H'AA]
ADDRn L
[H'40]
n = A to D
Figure 21.2 A/D Data Register Access Operation (Reading H'AA40)
Rev. 5.0, 09/03, page 665 of 806