SH7729R Datasheet, PDF (200/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

5.5 Usage Examples
5.5.1 Invalidating a Specific Entry
A specific cache entry can be invalidated by accessing the allocated memory cache and writing a 0
to the entry’s U and V bits. The A bit is cleared to 0, and an address is specified for the entry
address and the way. If the U bit of the way of the entry in question was set to 1, the entry is
written back and the V and U bits specified by the write data are written to.
In the following example, the write data is specified in R0 and the address is specified in R1.
; R0 = H'0000 0000 LRU = H'000, U = 0, V = 0
; R1 = H'F000 1080, Way = 1, Entry = H'08, A = 0
;
MOV.L R0, @R1
To invalidate all entries and ways, write 0 to the following addresses.
Addresses
F000 0000
F000 0010
F000 0020
:
F000 3FF0
This involves a total of 1,024 writes.
The above operation should be performed using a non-cacheable area.
Rev. 5.0, 09/03, page 154 of 806