SH7729R Datasheet, PDF (236/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 7.8 Interrupt Response Time
Number of States
Item
Peripheral
NMI
IRQ
PINT
Modules Notes
Time for priority
decision and SR
mask bit comparison
0.5 × Icyc
+ 0.5 × Bcyc
+ 0.5 × Pcyc
0.5 × Icyc
+ 1 × Bcyc
+ 4.5 ×
Pcyc^*4
0.5 × Icyc 0.5 × Icyc
+ 3.5 × Pcyc + 1.5 ×
Pcyc^*5
0.5 × Icyc
+ 3 × Pcyc^*6
Wait time until end
of sequence being
executed by CPU
X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc X (≥ 0) × Icyc Interrupt exception
handling is kept
waiting until the
executing instruc-
tion ends. If the
number of instruc-
tion execution
states is S^*1, the
maximum wait
time is: X = S – 1.
However, if BL is
set to 1 by instru-
ction execution or
by an exception,
interrupt exception
handling is
deferred until
completion of an
instruction that
clears BL to 0. If
the following
instruction masks
interrupt exception
handling, the
handling may be
further deferred.
Time from interrupt
exception handling
(save of SR and PC)
until fetch of first
instruction of
exception handler is
started
5 × Icyc
5 × Icyc
5 × Icyc
5 × Icyc
Rev. 5.0, 09/03, page 190 of 806