SH7729R Datasheet, PDF (163/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.5.6 MMU Exception in Repeat Loop
When an MMU exception or CPU address error occurs immediately before or within a repeat
loop, the PC of the instruction that generated the exception cannot be saved in SPC correctly and
the repeat loop cannot be restarted after returning from the exception handler. EXPEVT is set to
H'070 in cases of TLB miss, TLB invalid, and CPU address error. EXPEVT is set to H'0D0 in
case of TLB protection violation. Figure 3.14 shows where such cases occur.
In a repeat loop of 4 or more instructions, only the last 4 instructions are relevant (see figure 3.14
(4)).
(1) 1 instruction repeated (inst1, SR.RC=2)
inst-1
inst0
inst1
inst1
inst2
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
(2) 2 instructions repeated (inst1 and inst2, SR.RC=2)
inst-1
inst0
inst1
inst2
inst1
inst2
inst3
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
(3) 3 instructions repeated (inst1, inst2 and inst3, SR.RC=2)
inst-1
inst0
inst1
inst2
inst3
inst1
inst2
inst3
inst4
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
IF ID EX MA WB
: Exception source stage where SPC is not correct
and repeat loop can not be restarted
Figure 3.14 MMU Exception in Repeat Loop
Rev. 5.0, 09/03, page 117 of 806