SH7729R Datasheet, PDF (87/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

2.4 Instruction Formats
2.4.1 CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.12 Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Register
direct
Register
indirect
Instruction
Format Effective Address Calculation Method
Rn
Effective address is register Rn.
(Operand is register Rn contents.)
@Rn
Effective address is register Rn contents.
Rn
Rn
Register
@Rn+
indirect with
post-increment
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4 ₊
Register
@–Rn
indirect with
pre-decrement
1/2/4
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn − 1/2/4 _−
Rn − 1/2/4
Calculation
Formula
—
Rn
Rn
After instruction
execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4
→ Rn
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4
→ Rn
(Instruction
executed with Rn
after calculation)
1/2/4
Rev. 5.0, 09/03, page 41 of 806