SH7729R Datasheet, PDF (49/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Item
Features
Clock pulse
• Clock mode: Input clock can be selected from external input (EXTAL or
generator (CPG)
CKIO) or crystal oscillator
• Three types of clocks generated:
 CPU clock: 1–24 times the input clock, maximum 200 MHz
 Bus clock: 1–4 times the input clock, maximum 66.67 MHz
 Peripheral clock: 1/4–4 times the input clock, maximum 33.34 MHz
• Power-down modes:
 Sleep mode
 Standby mode
 Module standby mode
• One-channel watchdog timer
Memory
management
unit (MMU)
• 4 Gbytes of address space, 256 address spaces (8-bit ASID)
• Page unit sharing
• Supports multiple page sizes: 1 kbyte or 4 kbytes
• 128-entry, 4-way set associative TLB
• Supports software selection of replacement method and random-replacement
algorithms
Cache memory • 16-kbyte cache, mixed instruction/data
• 256 entries, 4-way set associative, 16-byte block length
• Write-back, write-through, LRU replacement algorithm
• 1-stage write-back buffer
• Maximum 2 ways of the cache can be locked
X/Y memory
• User-selectable mapping mechanism
 Fixed mapping for realtime applications (privileged DSP mode)
 Automatic mapping through TLB (user DSP mode)
• Three independent read/write ports
 8-/16-/32-bit access from the CPU
 Maximum two 16-bit accesses from the DSP
 8-/16-/32-bit and 16-byte access from the DMAC
• 8-kbyte RAM each for X and Y memory
Interrupt
• 7 external interrupt pins (NMI, IRQ5–IRQ0)
controller (INTC) _{• Level interrupt pins: 15 levels}
• 16 port interrupt pins (PINT15–PINT0)
• On-chip peripheral interrupts: Priority level set for each module
Rev. 5.0, 09/03, page 3 of 806