SH7729R Datasheet, PDF (470/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Compare Match Constant Register 0 (CMCOR0)
Compare match constant register 0 (CMCOR0) is a 16-bit register that sets the CMCNT0 compare
match period.
CMCOR0 is initialized to H'FFFF by a reset, but retains its previous value in standby mode.
Bit: 15
14
13
12
11
10
9
8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
12.4.3 Operation
Period Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in the CMCSR0 register and the
STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on the selected clock. When the
CMCNT counter value matches that of CMCOR0, the CMCNT0 counter is cleared to H'0000 and
the CMF flag in the CMCSR0 register is set to 1. The CMCNT0 counter begins counting up again
from H'0000.
Figure 12.27 shows the compare match counter operation.
CMCNT0 value
CMCOR0
Counter cleared by
CMCOR0 compare match
H'0000
Figure 12.27 Counter Operation
Time
Rev. 5.0, 09/03, page 424 of 806