SH7729R Datasheet, PDF (566/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Initialization
Clear TE and RE bits in SCSCR to 0
Set RIE, TIE, TEIE, MPIE, CKE1,
and CKE0 bits in SCSCR
(1)
(TE and RE are 0)
Set transmit/receive format in SCSMR (2)
Set value in SCBRR
(3)
Wait
Has a 1-bit
No
period elapsed?
Yes
Set TE and RE bits in SCSCR to 1
and set RIE, TIE, TEIE, and MPIE bits ⁽⁴⁾
End
Note: Numbers in parentheses refer to steps in the preceding procedure description.
Figure 15.18 Sample Flowchart for SCI Initialization
Transmitting Serial Data (Synchronous Mode): Figure 15.19 shows a sample flowchart for
transmitting serial data. The procedure for transmitting serial data is:
1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that
the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear
TDRE to 0.
2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if
it reads 1); if so, write data in SCTDR, then clear TDRE to 0.
Rev. 5.0, 09/03, page 520 of 806