SH7729R Datasheet, PDF (416/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Reload function: The value that was specified in the source address register can be
automatically reloaded every four DMA transfers. This function is only available in channel 2.
• Transfer requests
 External request (From two DREQ pins (channels 0 and 1 only). DREQ can be detected
either by edge or by level.)
 On-chip module request (Requests from on-chip peripheral modules such as serial
communications interface (IrDA and SCIF), A/D converter (A/D) and a timer (CMT). This
request can be accepted in all the channels.)
 Auto request (The transfer request is generated automatically within the DMAC.)
• Selectable bus modes: Cycle-steal mode or burst mode
• Selectable channel priority levels:
Fixed mode: The channel priority is fixed.
Round-robin mode: The priority of the channel in which the execution request was accepted is
made the lowest.
• Interrupt request: An interrupt request to the CPU can be generated after the specified number
of transfers.
Rev. 5.0, 09/03, page 370 of 806