SH7729R Datasheet, PDF (28/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section 16 Smart Card Interface...................................................................................... 533
16.1 Overview ........................................................................................................................... 533
16.1.1 Features ................................................................................................................ 533
16.1.2 Block Diagram ..................................................................................................... 534
16.1.3 Pin Configuration ................................................................................................. 535
16.1.4 Smart Card Interface Registers............................................................................. 535
16.2 Register Descriptions......................................................................................................... 536
16.2.1 Smart Card Mode Register (SCSCMR)................................................................ 536
16.2.2 Serial Status Register (SCSSR) ............................................................................ 537
16.3 Operation........................................................................................................................... 538
16.3.1 Overview .............................................................................................................. 538
16.3.2 Pin Connections.................................................................................................... 539
16.3.3 Data Format.......................................................................................................... 540
16.3.4 Register Settings................................................................................................... 541
16.3.5 Clock .................................................................................................................... 542
16.3.6 Data Transmission and Reception ........................................................................ 545
16.4 Usage Notes....................................................................................................................... 551
16.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode .................... 551
16.4.2 Retransmission (Receive and Transmit Modes) ................................................... 553
Section 17 Serial Communication Interface with FIFO (SCIF) ............................. 555
17.1 Overview ........................................................................................................................... 555
17.1.1 Features ................................................................................................................ 555
17.1.2 Block Diagram ..................................................................................................... 556
17.1.3 Pin Configuration ................................................................................................. 559
17.1.4 Register Configuration ......................................................................................... 560
17.2 Register Descriptions......................................................................................................... 561
17.2.1 Receive Shift Register (SCRSR) .......................................................................... 561
17.2.2 Receive FIFO Data Register (SCFRDR).............................................................. 561
17.2.3 Transmit Shift Register (SCTSR)......................................................................... 561
17.2.4 Transmit FIFO Data Register (SCFTDR) ............................................................ 562
17.2.5 Serial Mode Register (SCSMR) ........................................................................... 562
17.2.6 Serial Control Register (SCSCR) ......................................................................... 564
17.2.7 Serial Status Register (SCSSR) ............................................................................ 566
17.2.8 Bit Rate Register (SCBRR) .................................................................................. 571
17.2.9 FIFO Control Register (SCFCR).......................................................................... 578
17.2.10 FIFO Data Count Register (SCFDR) ................................................................... 580
17.3 Operation........................................................................................................................... 581
17.3.1 Overview .............................................................................................................. 581
17.3.2 Serial Operation.................................................................................................... 582
17.4 SCIF Interrupts .................................................................................................................. 594
17.5 Usage Notes....................................................................................................................... 595
Rev. 5.0, 09/03, page xxviii of xlvi