SH7729R Datasheet, PDF (582/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

16.2 Register Descriptions
This section describes the registers added for the smart card interface and the bits whose functions
are changed.
16.2.1 Smart Card Mode Register (SCSCMR)
The smart card mode register (SCSCMR) is an 8-bit readable/writable register that selects smart
card interface functions. SCSCMR bits 0, 2, and 3 are initialized to H'00 by a reset and in standby
mode.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
SDIR SINV
—
SMIF
Initial value: —
—
—
—
0
0
—
0
R/W: R
R
R
R
R/W R/W
R
R/W
Bits 7 to 4 and 1—Reserved: These bits are always read as 0. The write value should always be
0.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3: SDIR
0
1
Description
Contents of SCTDR are transferred LSB-first, and receive data is stored in
SCRDR LSB-first
(Initial value)
Contents of SCTDR are transferred MSB-first, and receive data is stored in
SCRDR MSB-first
Bit 2—Smart Card Data Inversion (SINV): Specifies whether to invert the logic level of the
data. This function is used in combination with bit 3 for transmitting and receiving with an inverse
convention card. SINV does not affect the logic level of the parity bit. See section 16.3.4, Register
Settings, for information on how parity is set.
Bit 2: SINV
0
1
Description
Contents of SCTDR are transferred unchanged, and receive data is stored
in SCRDR unchanged
(Initial value)
Contents of SCTDR are inverted before transfer, and receive data is
inverted before storage in SCRDR
Rev. 5.0, 09/03, page 536 of 806