SH7729R Datasheet, PDF (250/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.2.7 Break Data Mask Register B (BDMRB)
Bit: 31
30
29
28
27
26
25
24
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
19
18
17
16
BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
BDMRB is a 32-bit readable/writable register that specifies bits masked in the break data specified
by BDRB. BDMRB is initialized to H'00000000 by a power-on reset.
XYE = 0
XYE = 1
BDMB31–16
Mask L(I) DB31–16
Mask XDB15–0 (XYS = 0)
BDMB15–0
Mask L(I) DB15–0
Mask YDB15–0 (XYS = 1)
Bits 31–0:
BDMBn
Description
0
Break data BDBn of channel B is included in the break condition (Initial value)
1
Break data BDBn of channel B is masked and is not included in the break
condition
n = 31–0
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When a byte size is selected as a break condition, the break data must be set in bits
15-8 in BDRB for an even break address and bits 7-0 for an odd break address. Other
bits have no influence on a break condition.
Rev. 5.0, 09/03, page 204 of 806