SH7729R Datasheet, PDF (34/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Write-Back Buffer Configuration......................................................................... 150
Specifying Address and Data for Memory-Mapped Cache Access...................... 153
X/Y Memory Logical Address Mapping.............................................................. 159
X/Y Memory Physical Address Mapping ............................................................ 160
Block Diagram of INTC....................................................................................... 162
Example of IRL Interrupt Connection.................................................................. 166
Interrupt Operation Flowchart .............................................................................. 188
Example of Pipeline Operations when IRL Interrupt is Accepted ....................... 192
Block Diagram of User Break Controller............................................................. 195
When Interrupt Occurs before Branch Instruction is Executed ............................ 218
Canceling Standby Mode with STBCR.STBY..................................................... 235
Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output ......................... 238
Manual Reset STATUS Output............................................................................ 239
Standby to Interrupt STATUS Output.................................................................. 240
Standby to Power-On Reset STATUS Output...................................................... 241
Standby to Manual Reset STATUS Output.......................................................... 242
Sleep to Interrupt STATUS Output ...................................................................... 243
Sleep to Power-On Reset STATUS Output.......................................................... 243
Sleep to Manual Reset STATUS Output.............................................................. 244
Hardware Standby Mode (When CA Goes Low in Normal Operation)............... 246
Hardware Standby Mode Timing (When CA Goes Low during WDT
Operation on Standby Mode Cancellation) .......................................................... 247
Block Diagram of Clock Pulse Generator ............................................................ 250
Block Diagram of WDT ....................................................................................... 260
Writing to WTCNT and WTCSR......................................................................... 264
Points for Attention when Using Crystal Resonator............................................. 266
Points for Attention when Using PLL Oscillator Circuit ..................................... 267
Block Diagram of Bus State Controller................................................................ 271
Correspondence between Logical Address Space and Physical Address Space .. 275
Physical Space Allocation .................................................................................... 277
PCMCIA Space Allocation .................................................................................. 278
Writing to RFCR, RTCSR, RTCNT, and RTCOR............................................... 303
Basic Timing of Basic Interface ........................................................................... 315
Example of 32-Bit Data-Width Static RAM Connection ..................................... 316
Example of 16-Bit Data-Width Static RAM Connection ..................................... 317
Example of 8-Bit Data-Width Static RAM Connection ....................................... 318
Basic Interface Wait Timing (Software Wait Only)............................................. 319
Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal
WAITSEL = 1)..................................................................................................... 320
Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)........ 322
Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width) ........................... 323
Basic Timing for Synchronous DRAM Burst Read ............................................. 326
Synchronous DRAM Burst Read Wait Specification Timing .............................. 327
Rev. 5.0, 09/03, page xxxiv of xlvi