SH7729R Datasheet, PDF (342/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 11, 7, and 6—Area 5 Address OE/WE Assert Delay (A5TED2, A5TED1, A5TED0):
Specify the delay time from address output to OE/WE assertion for the PCMCIA interface
connected to area 5.
Bit 11:
A5TED2
0
1
Bit 7:
A5TED1
0
1
0
1
Bit 6:
A5TED0
0
1
0
1
0
1
0
1
Description
0.5-cycle delay
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
(Initial value)
Bits 10, 5, and 4—Area 6 Address OE/WE Assert Delay (A6TED2, A6TED1, A6TED0): The
A6TED bits specify the delay time from address output to OE/WE assertion for the PCMCIA
interface connected to area 6.
Bit 10:
A6TED2
0
1
Bit 5:
A6TED1
0
1
0
1
Bit 4:
A6TED0
0
1
0
1
0
1
0
1
Description
0.5-cycle delay
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
(Initial value)
Rev. 5.0, 09/03, page 296 of 806