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SH7729R Datasheet, PDF (598/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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372 clock cycles
186 clock cycles
0
185
Base clock
371 0
185
371 0
Receive
data (RxD)
Synchro-
nization
sampling
timing
Data
sampling
timing
Start
bit
D0
D1
Figure 16.8 Receive Data Sampling Timing in Smart Card Mode
The receive margin is found from the following equation:
For smart card mode:
M=
(0.5
â
1
2N
)
â
(L
â
0.5)F
â
D â 0.5
N
(1 + F)
à 100%
Where:
M = Receive margin (%)
N = Ratio of bit rate to clock (N = 372)
D = Clock duty (D = 0 to 1.0)
L = Frame length (L = 10)
F = Absolute value of clock frequency deviation
Using this equation, the receive margin when F = 0 and D = 0.5 is as follows:
M = (0.5 â 1/2 Ã 372) Ã 100% = 49.866%
Rev. 5.0, 09/03, page 552 of 806
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