SH7729R Datasheet, PDF (14/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Section
Page
11.2.13 MCS0 Control 304
Register (MCSCR0)
11.3.4 Synchronous 334
DRAM Interface
11.3.7 Waits between 363
Access Cycles
Figure 11.40 Waits
between Access Cycles
Description
Description added
Bit 6—CS2/CS0 Select (CS2/0)
Note that the CS2/0 bit in MCSCR should always be cleared to 0
(area 0 selected).
Bank Active description added
… .In bank active mode, too, all banks become inactive after a
refresh cycle or after the bus is released as the result of bus
arbitration.
The bank active mode should not be used unless the bus width
for all areas is 32 bits.
Figure amended
T₁
T₂ Twait T₁
T₂ Twait T₁
T₂
CKIO
A25 to A0
11.3.10 MCS[0] to
MCS[7] Pin Control
12.6 Usage Notes
14.4.3 Precautions
when Using RTC
Module Standby
366 Description amended
This enables 32-, 64-, 128-, or 256-Mbit memory to be connected
to area 0 or area 2. However, only CS2/0 = 0 (area 0) should be
used for MCSCR0. Table 11.15 shows MCSCR0–MCSCR7
settings and MCS[0]–MCS[7] assertion conditions.
431, Description added
432 _{13. DMAC transfers should not be performed in the sleep mode}
under conditions other than when the clock ratio of Iφ (on-
chip clock) to Bφ (bus clock) is 1:1.
14. When the following three conditions are all met, the
frequency control register (FRQCR) should not be changed
while a DMAC transfer is in progress.
• Bits IFC2 to IFC0 are changed.
• STC2 to STC0 in FRQCR are not changed.
• The clock ratio of Iφ (on-chip clock) to Bφ (bus clock) after
the change is other than 1:1.
15. If the following three conditions are all met, big-endian
access is used when the DMAC is used to transfer data from
XY memory, even in the little-endian mode.
• The source address for the transfer is in XY memory.
• The indirect address mode is used.
• The byte size data is transferred.
• The data format is little-endian.
470 Newly added
Rev. 5.0, 09/03, page xiv of xlvi