SH7729R Datasheet, PDF (216/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 7.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)
Interrupt Source
NMI
UDI
IRQ IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
PINT PINT0-7
PINT8-15
DMAC DEI0
DEI1
DEI2
DEI3
IrDA ERI1
RXI1
BRI1
TXI1
SCIF ERI2
RXI2
BRI2
TXI2
ADC ADI
TMU0 TUNI0
TMU1 TUNI1
TMU2 TUNI2
TICPI2
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
Priority
within IPR Default
Setting Unit Priority
H'1C0 (H'1C0)
16
—
—
High
H'5E0 (H'5E0)
H'200–3C0^* (H'600)
H'200–3C0^* (H'620)
H'200–3C0^* (H'640)
H'200–3C0^* (H'660)
H'200–3C0^* (H'680)
H'200–3C0^* (H'6A0)
H'200–3C0^* (H'700)
H'200–3C0^* (H'720)
H'200–3C0^* (H'800)
H'200–3C0^* (H'820)
H'200–3C0^* (H'840)
H'200–3C0^* (H'860)
H'200–3C0^* (H'880)
H'200–3C0^* (H'8A0)
H'200–3C0^* (H'8C0)
H'200–3C0^* (H'8E0)
H'200–3C0^* (H'900)
H'200–3C0^* (H'920)
H'200–3C0^* (H'940)
H'200–3C0^* (H'960)
H'200–3C0^* (H'980)
15
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
0–15 (0)
—
—
IPRC (3–0) —
IPRC (7–4) —
IPRC (11–8) —
IPRC (15–12) —
IPRD (3–0) —
IPRD (7–4) —
IPRD (15–12) —
IPRD (11–8) —
IPRE (15–12) High
Low
IPRE (11–8) High
IPRE (7–4)
Low
High
Low
IPRE (3–0) —
H'400 (H'400)
0–15 (0)
IPRA (15–12) —
H'420 (H'420)
0–15 (0)
IPRA (11–8) —
H'440 (H'440)
0–15 (0)
IPRA (7–4) High
H'460 (H'460)
Low
Low
Rev. 5.0, 09/03, page 170 of 806