SH7729R Datasheet, PDF (421/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

12.2 Register Descriptions
12.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the
next source address.
To transfer data in 16 bits or in 32 bits, specify a 16-bit or 32-bit address boundary address. When
transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source
address value. Operation is not guaranteed if other addresses are specified.
The initial value is undefined in a reset. The previous value is retained in standby mode.
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
…
0
…
Initial value: —
—
—
—
…
—
R/W: R/W R/W R/W R/W
…
R/W
Rev. 5.0, 09/03, page 375 of 806