SH7729R Datasheet, PDF (162/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

MMU Exception in Data Access Mode
TLB-related exception signals in a data access
IF ID EX MA WB
IF ID EX ^MA WB
IF ID EX MA WB
ID EX MA WB
ID EX MA
ID EX
MMU exception handler
: Exception source stage
: Stage cancellation for instruction
that has begun execution
WB
MA WB
Handler transition
processing
NOP
NOP
IF ID EX MA WB
IF
ID
EX
MA
WB
NOP
= Instruction fetch
= Instruction decode
= Instruction execution
= Memory access
= Write back
= No operation
Figure 3.13 MMU Exception Signals in Data Access
Rev. 5.0, 09/03, page 116 of 806