SH7729R Datasheet, PDF (436/855 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

source of the transfer request does not have to be the data transfer source or destination. When
RXI is set as the transfer request, however, the transfer source must be the SCI's receive data
register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the
SCI's transmit data register (TDR). If the transfer requester is the A/D converter, the data transfer
source must be the A/D data register.
Table 12.4 Selecting On-Chip Peripheral Module Request Modes with RS Bits
DMA
Transfer
Request
RS3 RS2 RS1 RS0 Source
Desti-
DMA Transfer Request Signal Source nation Bus Mode
1 0 1 0 IrDA
TXI1 (IrDA transmit-data-empty Any^* TDR1 Cycle-steal
transmitter interrupt transfer request)
1 0 1 1 IrDA
RXI1 (IrDA receive-data-full
receiver interrupt transfer request)
RDR1 Any^* Cycle-steal
1 1 0 0 SCIF
TXI2 (SCIF transmit-data-empty Any^* TDR2 Cycle-steal
transmitter interrupt transfer request)
1 1 0 1 SCIF
RXI2 (SCIF receive-data-full
receiver interrupt transfer request)
RDR1 Any^* Cycle-steal
1 1 1 0 A/D
ADI (A/D conversion end
converter interrupt)
ADDR Any^* Cycle-steal
1 1 1 1 CMT
CMI (Compare match timer
interrupt)
Any^*
Any^* Burst/
cycle-steal
ADDR: A/D data register of A/D converter
Note: * External memory, memory-mapped external device, on-chip peripheral module (excluding
DMAC, BSC, UBC)
When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt
enable bits must be set to output the interrupt signals.
If the interrupt request signal of the on-chip peripheral module is used as a DMA transfer request
signal, an interrupt is not sent to the CPU.
The DMA transfer request signals in table 12.4 are automatically discontinued when the
corresponding DMA transfer is performed. If cycle-steal mode is being employed, they are
withdrawn at the first transfer; if burst mode is being used, they are discontinued at the last
transfer.
Rev. 5.0, 09/03, page 390 of 806